VLSI數位訊號處理架構設計

Good understanding and design experience of VLSI signal processing algorithms and architecture and chips with applications to multimedia-communications systems through ASIC-, processor-, and GPU approaches.

數位電路設計導論, 訊號與系統

無備註

http://viplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall.htm Handout is available

1. 作業 2. 期中報告 3. 期末計畫

• Lecture 1: Introduction to Digital Signal Processing Systems

  1.Introduction 2.DSP algorithm

• Lecture 1: Introduction to Digital Signal Processing Systems

  1.Introduction 2.DSP algorithm

• Lecture 1: Introduction to Digital Signal Processing Systems

  1.Introduction 2.DSP algorithm

• Lecture 2: Iteration Bound

  1. Loop Bound and Iteration Bound 2. Compute the Iteration Bound 2.1 Longest Path Matrix Algorithm (LPM) 2.2 Minimum Cycle Mean Method (MCM)

• Lecture 3: Pipelining and parallel processing

  1. Pipelining of FIR Digital Filter Parallel Processing 2. Pipelining and Parallel Processing for Low Power

• Lecture 3: Pipelining and parallel processing

  1. Pipelining of FIR Digital Filter Parallel Processing 2. Pipelining and Parallel Processing for Low Power

• Lecture 4: Retiming

  1. Solving systems of inequelities 2. Retiming technique

• Lecture 5: Unfolding

  1. Algorithm and properties of unfolding

• Lecture 5: Unfolding

  2.Critical path, unfolding and retiming 3.Applications of unfolding

• Midterm Reprot

• Lecture 6: Folding

  1. Register minimization technique 2. Register minimization in folding architecture 3. Folding transformation

• Lecture 7: Algorithmic Strength Reduction in Filters and Transforms

  1. Review of First- and Second-Order Recursive Discrete Fourier Transform (DFT) Structures 2. New Recursive DFT/IDFT Algorithm and Architecture 3. Folded-Type DFT/IDFT Architecture and Implementation

• Lecture 8: Pipelined and Parallel Recursive and Adaptive Filters

  1. Pipeline interleaving in digital filter 2. Parallel processing for IIR filter 3. Pipelined adaptive digital filter

• Lecture 9: Low-Power CMOS VLSI Design Final Project Planning

  1. Low power process level design 2. Low power system level design

• Lecture 10: Programmable Digital Signal Processors Final Project Execution

  1. DSP processor for multimedia signal processing 2. DSP processor for wireless communication

• Lecture 11: Introduction to 3D Graphics Processing Flow Final Project Execution

  1. GPU pipeline 1.1 Vertex shader 1.2 Geometry shader 1.2 Fragment shader

• Lecture 12: Introduction to GPU Hardware Final Project Execution

  1. History of GPU Hardware 2. GPU Hardware Consideration Modern GPU Hardware Architecture 2.1 NVIDIA GeForce 2.2 AMD (ATI) Radeon 2.3 IMG PowerVR 2.4 ARM Mali

• Lecture 13: Geometry Subsystem Design Final Project Demo

  1. Geometry Subsystem 2. Introduction to Shading Algorithms 3. Proposed Low-Complexity Subdivision Algorithm 4. Proposed Power-Area Efficient Geometry Engine 5. Implementation and Comparison Results

K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. NY: Wiley, 1999. Reference Books: P. Pirsch, Architectures for Digital Signal Processing. NY: Wiley, 1998. ※請修課同學尊重智慧財產權!勿隨意過度影印教科書或使用未經授權之著作權與電腦軟體等。

地點

EC-419R

時間

Friday: CD

聯絡方式

ext 54815