軟硬體協同設計概論與實作(英文授課)
Introduction to Hardware-Software Codesign and Implementation
| 節 | 週二 | 週五 |
|---|---|---|
3 10:10–11:00 | 軟硬體協同設計概論與實作(英文授課) EC114（光復） 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 軟硬體協同設計概論與實作(英文授課) EC114（光復） |
* 根據陽明交大上課時間表所列
This course covers the principles and practices of hardware-software integration and co-design. In this course, students will learn how to analyze the behavior model of a complex system and to make design decisions on whether each sub-system should be implemented in hardware or software. A series of labs based on platform FPGAs will be used to help students acquire solid experiences on co-design.
It is required that you have taken the following courses: Digital Circuit Designs and Digital Circuit Labs. It is also recommended that you have some knowledge on Computer Organization. The labs will require Verilog and C programming extensively.
無備註
The teaching materials will be available on the E3 website.
The grading of this course is based on seven labs (70%) and one final projects (30%).
Introduction to complex system design.
- 講授：
- 3
Principles of hardware-software co-design.
- 講授：
- 6
System models and architecture.
- 講授：
- 6
Hierarchy of complex system software.
- 講授：
- 6
Target technologies of system hardware.
- 講授：
- 9
Co-design strategies: from models to implementations.
- 講授：
- 6
Verification and debugging of a co-designed system.
- 講授：
- 6
| 週次 | 主題 |
|---|---|
| 第 1 週 | Understanding the co-design platform: Xilinx Zynq-7000. 2/23 2/27 |
| 第 2 週 | Understanding the co-design platform: Xilinx Zynq-7000. 3/2 3/6 |
| 第 3 週 | Profiling a system behavior. 3/9 3/13 |
| 第 4 週 | Simple hardware IP implementation: Adding a hardware IP to the system (using Verilog and the FPGA implementation flow). 3/16 3/20 |
| 第 5 週 | Simple hardware IP implementation: Adding a hardware IP to the system (using Verilog and the FPGA implementation flow). 3/23 3/27 |
| 第 6 週 | HW-SW communication using a simple memory-mapped interface (using jointly C/Verilog). 3/30 4/3 |
| 第 7 週 | HW-SW communication using a simple memory-mapped interface (using jointly C/Verilog). 3/29 3/31 |
| 第 8 週 | Interrupt-driven HW-SW communication interface (using jointly C/Verilog). 4/10 4/13 |
| 第 9 週 | Interrupt-driven HW-SW communication interface (using jointly C/Verilog). 4/17 4/20 |
| 第 10 週 | Master IP interface implementation: application-specific DMA (using jointly C/Verilog). 4/24 4/27 |
| 第 11 週 | Master IP interface implementation: application-specific DMA (using jointly C/Verilog). 5/1 5/4 |
| 第 12 週 | Usage of on-chip memory (using jointly C/Verilog). 5/8 5/11 |
| 第 13 週 | Usage of on-chip memory (using jointly C/Verilog). 5/15 5/18 |
| 第 14 週 | Optimization of a hardware IP (using jointly C/Verilog). 5/22 5/25 |
| 第 15 週 | Optimization of a hardware IP (using jointly C/Verilog). 5/24 5/26 |
| 第 16 週 | Final project: HW-SW codesign competition (using jointly C/Verilog). 5/29 6/1 |
| 第 17 週 | Final project. 6/5 6/8 |
None.
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