低功率積體電路設計
Low Power IC Design
| 節 | 週二 |
|---|---|
2 09:00–09:50 | 低功率積體電路設計 EE116(光復) 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
Low-power circuit design is one of the critical design challenges for high-performance computing, mobile devices, IoT devices and biomedical applications. Thus, the goal of this course is to introduce low-power design techniques of nano-scale ICs from circuit-level, architecture-level to system-level, particularly emphasizing on low-voltage design. Currently, low-voltage design has been attracted huge attention from the industry of IC design. Additionally, advanced AI-related circuits will be also discussed in this course.
Electronics, VLSI Design
無備註
https://sites.google.com/site/nctueecslab/
1. Class Participation (10% ) 2. Exercises (20% ) 3. Midterm Proposal for your final report (15% ) 4. Final Exam (20% ) 5. Final Project Presentation (10% ) 6. Final Project Report (25% )
Introduction to low power IC design
Introduce the importance of low-power applications and design challenges of low-power circuits
- 講授:
- 3
Overview of nano-scale CMOS digital circuits
Review IC design abstraction level and design flow, and introduce the design challenges of nano-scale CMOS digital circuits
- 講授:
- 4.5
Power reduction techniques
Introduce various power reduction techniques, including static-power, dynamic-power, design-phase and run-time power reduction techniques
- 講授:
- 4.5
Energy-efficient architecture
Analyze the design trade-off among power, performance and area in architecture-level
- 講授:
- 4.5
Low-voltage design
Introduce low-voltage circuit design (near-threshold and sub-threshold) and the corresponding design challenges
- 講授:
- 4.5
Power management
Discuss the power control circuits and power management methods for dynamic voltage and frequency scaling (DVFS) systems
- 講授:
- 4.5
Low-power memory circuits and memory systems
Introduce the power analysis and low-power design of memory circuits and memory systems
- 講授:
- 4.5
Timing control for low-power Circuits
Present timing-tolerant, self-timed and asynchronization circuits for low-power circuits
- 講授:
- 4.5
Variation-tolerant circuit design
Discuss the variation-aware or variation-tolerant design techniques for advanced technologies
- 講授:
- 4.5
Advanced AI-related circuits and architectures
Introduce to AI-related circuits and architectures, such as spike neural network, deep learning, convolution neural network
- 講授:
- 4.5
Low-power design methodology and I/O interface
Review low-power design methodology and multi-mode multi-corner (MMMC) optimization
- 講授:
- 3
教師未提供此項資料
1. Class notes 2. Digital Integrated Circuits, by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 3. Integrated circuit design, by Neil Weste and David Harris
- 地點
- MIRC 301
- 時間
- After class or by appointment
- 聯絡方式
- By email
