邏輯設計(英文班)
Logic Design
| 節 | 週二 | 週五 |
|---|---|---|
2 09:00–09:50 | 邏輯設計(英文班) ED101（光復） | |
5 13:20–14:10 | 邏輯設計(英文班) ED101（光復） 2 節連堂 | |
6 14:20–15:10 |
* 根據陽明交大上課時間表所列
Learn and apply the switching theory to the solution of logic design problems.
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Class website: http://tiger.ee.nctu.edu.tw/Course.php
Quiz 10% Homework 20% Mid-term Exam 35% Final Exam 35%
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | Unit 0 Introduction Unit 1 Number Systems and Conversion 2/22 2/23 |
| 第 2 週 | Unit 2 Boolean Algebra 3/1, 3/2 |
| 第 3 週 | Unit 3 Boolean Algebra (cont'd) 3/8, 3/9 |
| 第 4 週 | Unit 4 Applications of Boolean Algebra 3/15, 3/16 |
| 第 5 週 | Unit 5 Karnaugh Maps 3/22, 3/23 |
| 第 6 週 | Unit 7 Multi-Level Gate Circuits 3/29, 3/30 |
| 第 7 週 | Unit 8 Combinational Circuit Design 4/5, 4/6 |
| 第 8 週 | Unit 9 Multiplexers Decoders and PLD + Review 4/12, 4/13 |
| 第 9 週 | Midterm 4/19 |
| 第 10 週 | Unit 11 Latches and Flip-Flops 4/26, 4/27 |
| 第 11 週 | Unit 12 Registers and Counters 5/3, 5/4 |
| 第 12 週 | Unit 13 Analysis of Clocked Sequential Circuits 5/10, 5/11 |
| 第 13 週 | Review 5/17, 5/18 |
| 第 14 週 | Unit 14 Derivation of State Graphs and Tables 5/24, 5/25 |
| 第 15 週 | Unit 15 Reduction of State Tables 5/31, 6/1 |
| 第 16 週 | Unit 16 Sequential Circuit Design 6/7, 6/8 |
| 第 17 週 | Review 6/14, 6/15 |
| 第 18 週 | Final 6/21 |
C. H. Roth, Jr. and L. Kinney, Fundamentals of Logic Design, 6th edition, Cengage, 2010.
- 地點
- ED 601
- 時間
- 1:30~3:30pm, Wed
- 聯絡方式
- ext. 31671 email: mango@faculty.nctu.edu.tw