數位系統設計

Digital Systems Design

學期

107-1

學分

0 學分

當期課號

1169

永久課號

DCP1172

開課單位

資訊工程學系

授課教師

單智君

校區

光復

類別

選修

上課時間表

節	週二	週五
2 09:00–09:50	數位系統設計 EC115（光復）
5 13:20–14:10		數位系統設計 EC115（光復） 2 節連堂
6 14:20–15:10		數位系統設計 EC115（光復） 2 節連堂

* 根據陽明交大上課時間表所列

概述

本課程以數位電路的知識為基礎,探討數位系統的原理與設計,並包含許多數位系統設計實例。

先修科目

Digital Circuit Design ( or Logic Design), Verilog

備註

無備註

教學方式

課程相關資料與訊息(如:講義、進度、公告等)公佈在網路教學平台 http://dcpc.nctu.edu.tw

評分方式

Homework/Lab Units/Project Examinations Class Participation

課程大綱

Review of Logic Design Fundamentals

Combinational Logic Boolean Algebra Gate-Level Minimization Hazards in Combinational Circuits Latches and Flip-Flops Synchronous Sequential Circuits Sequential Circuit Timing Tristate Logic and Buses

講授：

3
Introduction to Verilog

Computer-Aided Design Hardware Description Languages Verilog Description of Combinational Circuits Verilog Description of Sequential Circuits Testing a Verilog Model

講授：

3
Introduction to Programmable Logic Devices

Brief Overview of Porgrammable Logic Devices Simple Porgrammable Logic Devices (SPLDs) Complex Porgrammable Logic Devices (CPLDs) Field-Programmable Gate Arrays (FPGAs)

講授：

3
Design Examples

Examples of Combinational Circuits Examples of Sequential Circuits

講授：

6
State Machine Charts and Microprogramming

State Machine Charts Derivation of SM Charts Realization of SM Charts Microprogramming Linked State Machines

講授：

6
Designing with Field Programmable Gate Arrays

Implementing Functions in FPGAs Shannon's Decomposition Carry Chains and Cascade Chains in FPGAs Dedicated Memory and Multipliers in FPGAs Design Translation (Synthesis) Mapping, Placement, and Routing

講授：

6
Floating-Point Arithmetic

Representation of Floating-Point Numbers Floating-Point Multiplication Floating-Point Addition Other Floating-Point Operations

講授：

3
Additional Topics in Verilog

Verilog Functions Verilog Tasks Multivalued Logic and Signal Resolution Built-in and User-Defined Primitives SRAM Model Named Association Generate Statements System FUnctions Compiler Directives File I/O Functions Timing Checks

講授：

6
Design of a RISC Microprocessor

The RISC Philosophy The MIPS ISA MIPS Instruction Encoding Implementation of a MIPS Subset Verilog Model

講授：

6
Hardware Testing and Design for Testability

Testing Combinational Logic Testing Sequential Logic Scan Testing Boundary Scan Built-In Self-Test

講授：

3
Project Presentation

講授：

3

週次計畫

週次	主題
第 1 週	Syllabus Review of Logic Design Fundamental
第 2 週	Introduction to Verilog
第 3 週	Introduction to Programmable Logic Devices
第 4 週	Design Examples
第 5 週	Design Examples
第 6 週	State Machine Charts and Microprogramming
第 7 週	State Machine Charts and Microprogramming
第 8 週	Exam#1
第 9 週	Designing with Field Programmable Gate Arrays
第 10 週	Designing with Field Programmable Gate Arrays
第 11 週	Floating-Point Arithmetic
第 12 週	Additional Topics in Verilog
第 13 週	Additional Topics in Verilog
第 14 週	Design of a RISC Microprocessor
第 15 週	Design of a RISC Microprocessor
第 16 週	Hardware Testing and Design for Testability
第 17 週	Project Presentation
第 18 週	Exam#2

教科書

References: 1. Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning. 2. M. Morris Mano, Charles R. Kime, and Tom Martin, Logic and Computer Design Fundamentals, 5th Edition, 2016, Pearson Prentice Hall.

Office Hours

地點: EC516
時間: 開學後討論再定
聯絡方式: Tel: ext.31832 E-mail: jjshann@cs.nctu.edu.tw