模式化通訊IC設計
Model-based Communication IC Design
| 節 | 週二 |
|---|---|
2 09:00–09:50 | 模式化通訊IC設計 ED814（光復） 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
The objective of this course is to introduce a new IC design flow, ie., model-based communication IC design. This flow works with Simulink blocks and the HDL coder by Mathworks. The distinct feature is that RTL codes can be generated by Simulink blocks. Students will learn how a communication IC can be designed with the synthesizable blocks in the Simulink library. Finally, experiments with Zedboard/AD9361 will be conducted to verify the validity of the designed ICs.
Digital communications, Digital signal processing
無備註
All course materials will be given.
1.學期作業、考試、評量 Homework Assignments 20% Two Exams 50% Experiments and projects 30%
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 0 週 | Part I: background |
| 第 0 週 | Part II: Hardware architecture |
| 第 0 週 | Part III: Transceiver design and experiment |
| 第 1 週 | Digital communication systems |
| 第 2 週 | HDL I |
| 第 3 週 | HDL II |
| 第 4 週 | HDL III |
| 第 5 週 | Introduction to Simulink/Matlab |
| 第 6 週 | Filter architectures |
| 第 7 週 | Fixed-point computations |
| 第 8 週 | Trigonometric function computations |
| 第 9 週 | State machine design |
| 第 10 週 | Midterm |
| 第 11 週 | QPSK transmitter design |
| 第 12 週 | QPSK receiver design: phase-locked loop |
| 第 13 週 | QPSK receiver design: timing recovery |
| 第 14 週 | QPSK receiver design: carrier recovery |
| 第 15 週 | Experiment 1: introduction to Xilinx Zynq 7000 FPGA/AD9361 |
| 第 16 週 | Experiment 2: QPSK transmission with Simulink models |
| 第 17 週 | Experiment 3: OPSK transmission with FPGA |
| 第 18 週 | Final |
教師未提供此項資料
- 地點
- 教師未提供此項資料
- 時間
- 教師未提供此項資料
- 聯絡方式
- Email: wrwu@faculty.edu.tw Phone: 31647