數位信號處理超大型積體電路
VLSI Digital Signal Processing
| 節 | 週四 |
|---|---|
3 10:10–11:00 | 數位信號處理超大型積體電路 EE116（光復） 3 節連堂 |
4 11:10–12:00 | |
N 12:20–13:10 |
* 根據陽明交大上課時間表所列
Digital VLSI design and implementation for various signal processing systems from an architecture point of view.
Signals and Systems Logic Design
無備註
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Homework/Assignments: 40% Midterm: 25% Final: 35%
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction to Digital Signal Processing Systems 9/13 |
| 第 2 週 | Iteration Bound 9/20 |
| 第 3 週 | Digital Filters 9/27 |
| 第 4 週 | Pipelined and Parallel Processing 10/4 |
| 第 5 週 | Retiming & Unfolding 10/11 |
| 第 6 週 | Retiming & Unfolding 10/18 |
| 第 7 週 | Folding 10/25 |
| 第 8 週 | Folding 11/1 |
| 第 9 週 | Midterm 11/8 |
| 第 10 週 | Pipelined and Parallel Recursive and Adaptive Filters 11/15 |
| 第 11 週 | CORDIC, Divider, Square Root 11/22 |
| 第 12 週 | Scaling and Round-off Noise 11/29 |
| 第 13 週 | Energy and Delay Models 12/6 |
| 第 14 週 | Circuit Optimization 12/13 |
| 第 15 週 | Wordlength Optimization 12/20 |
| 第 16 週 | Architectural Optimization 12/27 |
| 第 17 週 | Review 1/3 |
| 第 18 週 | Final Exam 1/10 |
1. VLSI Digital Signal Processing Systems: Design and Implementation, Keshab K. Parhi, 1st edition, Wiley-Interscience, 1999. 2. DSP Architecture Design Essentials, Dejan Markovic and Robert W Brodersen, 1st edition, Springer, 2012.
- 地點
- MIRC R301
- 時間
- By appointment
- 聯絡方式
- yck.nctu@gmail.com