數位電路設計(英文授課)
Digital Circuit Design
| 節 | 週三 | 週五 |
|---|---|---|
3 10:10–11:00 | 數位電路設計(英文授課) EC115（光復） 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 數位電路設計(英文授課) EC115（光復） |
* 根據陽明交大上課時間表所列
本課程目標是介紹數位系統如數位電子計算機中所使用數位電路的邏輯設計的基礎觀念以及使用的基本工具。內容包括:數位系統與二進數字、布林代數與邏輯閘、閘層次最簡化、組合邏輯、同步循序邏輯、以及暫存器與計數器。 This course is aimed at introducing the fundamental concepts and the basic tools used in the logic design of digital circuits in digital systems such as a digital electronic computer. Contents include: Digital Systems and Binary Numbers, Boolean Algebra and Logic Gates, Gate-Level Minimization, Combinational Logic, Synchronous Sequential Logic, and Registers and Counters.
無/nil
無備註
教學以課堂講授為主;課程相關資料與訊息將利用e3網路教學平台傳遞 This course will be conducted through classroom lectures. Related materials and information will be posted on campus e3 website
1. 三次正式筆試,每次涵蓋課程1/3內容,於學期第六、十二及十八週的週三課堂上舉行。 2. 評分方式:平時抽考及課堂表現:25%;正式考試:25%×3=75%。(以上僅為建議;將與修課同學商定之。) 1. Three formal written examinations, each covering a third of the course contents, and are to be taken in the Wednesday class sessions in the 6th, 12th, and 18th week of the semester. 2. Grading policy: Pop quizzes and in-class performance 25%; formal written exams 25%×3=75%. (Above is suggestion only, and is to be finalized with class attendees.)
Boolean Algebra and Logic Gates
1. Basic Theorems and Properties of Boolean Algebra 2. Boolean Functions 3. Canonical and Standard Forms 4. Digital Logic Gates
- 講授：
- 6
Gate-Level Minimization
1. The Map Method 2. Product-of-Sums Simplification 3. Don't-Care Conditions 4. Two-level Logic Implementations
- 講授：
- 9
Combinational Logic
1. Combinational Circuits 2. Combinational Circuits Design Procedure 3. Binary Adder-Subtractor / Decimal Adder 4. Binary Multiplier 5. Decoder/Encoder/Multiplexer
- 講授：
- 6
Synchronous Sequential Logic
1. Sequential Circuits 2. Latches and Flip-Flops 3. State Machine Models 4. State Reduction and Assignment 5. Sequential Circuits Design Procedure
- 講授：
- 7
Registers and Counters
1. Registers 2. Shift Register 3. Ripple Counter 4. Synchronous Counter 5. Ring Counter
- 講授：
- 6
Memory and Programmable logic
1. Memory Devices 2. Memory Address Decoding 3. Error Detection and Correction 4. ROM and Logic Implementations 5. Programmable Logic Array
- 講授：
- 7
Design at the Register Transfer Level
1. Register Transfer Level Notation 2. Register Transfer Level in HDL 3. Algorithmic State Machines (ASMs) Example and HDL Description 4. Sequential Binary Multiplier and Its Control Logic 5. Design with Multiplexers
- 講授：
- 3
Digital Systems and Binary Numbers
1. Digital Systems 2. Binary Numbers 3. Number-Base Conversions 4. Binary Logic
- 講授：
- 4
| 週次 | 主題 |
|---|---|
| 第 1 週 | Chapter 1 Digital Systems and Binary Numbers 2019/2/20(三)CD-EC115 2019/2/22(五)G-EC115 |
| 第 2 週 | Chapter 1 Digital Systems and Binary Numbers Chapter 2 Boolean Algebra and Logic Gates 2019/2/27(三)CD-EC115 2019/3/1(五)G-EC115 |
| 第 3 週 | Chapter 2 Boolean Algebra and Logic Gates 2019/3/6(三)CD-EC115 2019/3/8(五)G-EC115 |
| 第 4 週 | Chapter 2 Boolean Algebra and Logic Gates Chapter 3 Gate-Level Minimization 2019/3/13(三)CD-EC115 2019/3/15(五)G-EC115 |
| 第 5 週 | Chapter 3 Gate-Level Minimization 2019/3/20(三)CD-EC115 2019/3/22(五)G-EC115 |
| 第 6 週 | Examination I Chapter 3 Gate-Level Minimization 2019/3/27(三)CD-EC115 2019/3/29(五)G-EC115 |
| 第 7 週 | Chapter 3 Gate-Level Minimization 2019/4/3(三)CD-EC115 2019/4/5(五)G-EC115 |
| 第 8 週 | Chapter 4 Combinational Logic 2019/4/10(三)CD-EC115 2019/4/12(五)G-EC115 |
| 第 9 週 | Chapter 4 Combinational Logic 2019/4/17(三)CD-EC115 2019/4/19(五)G-EC115 |
| 第 10 週 | Chapter 5 Synchronous Sequential Logic 2019/4/24(三)CD-EC115 2019/4/26(五)G-EC115 |
| 第 11 週 | Chapter 5 Synchronous Sequential Logic 2019/5/1(三)CD-EC115 2019/5/3(五)G-EC115 |
| 第 12 週 | Examination II Chapter 5 Synchronous Sequential Logic 2019/5/8(三)CD-EC115 2019/5/10(五)G-EC115 |
| 第 13 週 | Chapter 6 Registers and Counters 2019/5/15(三)CD-EC115 2019/5/17(五)G-EC115 |
| 第 14 週 | Chapter 6 Registers and Counters 2019/5/22(三)CD-EC115 2019/5/24(五)G-EC115 |
| 第 15 週 | Chapter 7 Memory and Programmable logic 2019/5/29(三)CD-EC115 2019/5/31(五)G-EC115 |
| 第 16 週 | Chapter 7 Memory and Programmable logic 2019/6/5(三)CD-EC115 2019/6/7(五)G-EC115 |
| 第 17 週 | Chapter 7 Memory and Programmable logic Chapter 8 Design at the Register Transfer Level 2019/6/12(三)CD-EC115 2019/6/14(五)G-EC115 |
| 第 18 週 | Examination III Chapter 8 Design at the Register Transfer Level 2019/6/19(三)CD-EC115 2019/6/21(五)G-EC115 |
M. Morris Mano and Michael D. Ciletti, “Digital Design with An Introduction to The Verilog HDL,” 5th ed., 2013, Pearson Education Limited (or the similar)
- 地點
- EC524 and TA's offices
- 時間
- 上課後再與修課學生議定之 To be determined with course attendees
- 聯絡方式
- (03)573-1828 (or campus extension 31828) cpchung@cs.nctu.edu.tw Campus e3 website