積體電路設計實驗

This course aims to convey the senior and graudate EE students techniques to design VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone. The course starts from system design specs of an application which demands the need of developing specific hardwares or application specific integrated circuits (ASIC), SoCs or application processors with integrated sensors. Then followed by the presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL, designers can describe their designs either in behavioral level or structural level. Before going down to the lower level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before fabrication. 電子研究所希望培育學生具備十項核心能力及三項基本素養(請參官網http://www.ee.nctu.edu.tw首頁之【學術研究】→【IEET】內容。 ※本課程將培育學生具備下述幾項核心能力: 1.1 固態電子或電路系統相關專業知識之能力 1.2 固態電子或電路系統之設計、實驗及分析數據之能力,並具有發掘、分析、獨立解決問題及創新思考的能力 1.3 使用電腦輔助軟體、儀器等工具的能力 1.4 具跨領域整合之能力 2.1 理解並實踐專業倫理與社會責任之能力 2.2 具規劃、領導與實行團隊合作之能力 3.1 瞭解國內外電子資訊產業脈動 ※本課程將培育學生具備下述幾項基本素養: 1 養成學生具備電子工程基礎與專業知識,並配合實作,達到理論與實務相結合之目的。使學生具備推論、分析、創新及整合能力。 2 教育學生具備寬廣之知識、溝通技巧與團隊精神,以迎接不同生涯發展之挑戰。教育學生瞭解專業倫理及社會責任。 3 建立國際化學習環境,使學生洞察國內外社會與產業之脈動,以培養學生成為立足於全球之電子菁英與領袖人才。

Introduction to VLSI

無備註

Lecture at ED415 Lab at ED415

作業部份: 12 Lab. Exercises Midterm and Final Projects 考試部份: Project-based with On-line Tests. Quiz 評量部份: 12 Lab. Exercises (60%) Homeworks and Project (30%) On-Line Test (10%) Total score is 100%

• Introduction + Workstation Command

  講授：

  3

  實作：

  5

• Combinational Circuits Design

  講授：

  3

  實作：

  5

• Sequential Circuits Design

  講授：

  3

  實作：

  5

• Testbench programming and Designware

  講授：

  3

  實作：

  5

• Coding Style, Macro Behavior and nLint

  講授：

  3

  實作：

  5

• Coverage and System Verilog Assertion

  講授：

  3

  實作：

  5

• Introduction to Synthesis Flow with Synopsys Design Compiler

  講授：

  3

  實作：

  5

• Static Timing Analysis

  講授：

  3

  實作：

  5

• Gate-level Simulation

  講授：

  4

  實作：

  6

• Low Power Design

  講授：

  4

  實作：

  6

• Cell-Based APR Design Flow

  講授：

  4

  實作：

  6

• Standard Cell Library, Hard Macro, Post-layout Verification, Power Analysis

  講授：

  4

  實作：

  6

• DFT/DFM/PrimeTime

  講授：

  3

  實作：

  5

(1) "Application-Specific Integrated Circuits" by Prof. M.J.S. Smith from University of Hawaii ( Addison-Wesley, 1997, ISBN 0-201-50022-1 ). This book covers a lot of design issues and related CAD tools which may interest readers and provide many details for reference. (2) "Principles of CMOS VLSI Design -- A Systems Perspective", by Neil H. Weste and Kamran Eshraghian ( 2nd Edition from Addison-Wesley Publishing Company, ISBN 0-201-53376-6 ).

地點

ED505

時間

Every Wed. Morning from 10:00AM to 12:00AM at ED505 Prefer making appointment via email.

聯絡方式

email: hcchang@si2lab.org ext.: 54134