計算機輔助設計特論

Computer-aided design (CAD) techniques are essential for modern complex designs. In this course, the CAD techniques for the synthesis and verification of VLSI designs are introduced. Besides using those CAD tools, our focus is the insight techniques and algorithms to develop the synthesis and verification tools. These contents are important background knowledge to do the related researches. For those students whose research directions are not CAD-related topics, better understanding of CAD tools also helps to use those tools better.

Prerequisites: Computer programming, Introduction to digital systems and VLSI design

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Midterm: 30%, Final: 30%, Projects: 40%

• Introduction to CAD techniques for design and verification

  講授：

  3hr

• Binary decision diagram (BDD)

  講授：

  3hr

• RTL synthesis & logic optimization

  講授：

  6hr

• Technology mapping & timing optimization

  講授：

  6hr

• System-level low-power design techniques

  講授：

  3hr

• Synthesis of analog circuits

  講授：

  6hr

• Verification methodology for SoC

  講授：

  3hr

• Coverage-driven functional verification methodology

  講授：

  3hr

• Formal verification techniques

  講授：

  3hr

• Analog/mixed-signal system verification

  講授：

  9hr

Reference Books: 1. Giovanni De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994. 2. Prakash Rashinkar, Peter Paterson, and Leena Singh, "System-on-a-chip Verification – Methodology and Techniques", Kluwer Academic Publishers, 2001. 3. L.-T. Wang, Y.-W. Chang, and K.-T. Cheng, "Electronic Design Automation: Synthesis, Verification, and Testing", Elsevier/Morgan Kaufmann, 2009.

地點

Office (ED-540)

時間

Thursday 1000-1200

聯絡方式

Email appointment is preferred.