矽奈米元件及物理
Silicon Nanometer Devices and Physics
| 節 | 週五 |
|---|---|
2 09:00–09:50 | 矽奈米元件及物理 ED203(光復) 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
The major subjects provided by this course will cover (1) Si CMOS scaling limitations and the physics in nanoscale (2) Si CMOS device design challenges due to scaling limitations (3) The solutions to extend Si CMOS technology in nanoscale era – new materials, new structures, and integration methods, targeted for devices an integrated ciruts. The major goal of this course aims at providing fundamental knowledge in nanoscale devices and most advanced technologies in nanoscale process integration for integrated circuits. The ultimate goal is to bring up the knowledge base of students in device physics, process integration, and material science, and further stimulate novel ideas and methods in realizing tremendous breakthrough in nanoscale electronics.
Semiconductor device physics, Modern physics, Semiconductor integrated circuit technology
無備註
TA : 周書緯 /chousw0804@gmail.com/0988-811-530 韋安迪Adhi Cahyo Wijaya/adhi.eed07g@nctu.edu.tw/0905032467
CreditMid-term exam. 40% Final exam. (or report)40% Class participation & quiz 20%
Chapter-1
Introduction1.1 1.1 Evolution of Si Technology 1.2 ITRS – International Technology Scaling Roadmap 1.3 Outlook of Nano-Technology- - Micro- and Nano-technology history- - Molecular electronic switch- - Rapid single flux quantum devices- - Spin resonance transistor and spintronics- - Single electron transistors
- 講授:
- 12
Chapter-2
Sub-100 nm CMOS Technology 2.1 SoC for Digital, Analog, MS and RF 2.2 Nanoscale CMOS scaling scenario 2.3 Nanoscale CMOS scaling solutions- - Gate stack – dielectric and electrode- - Ultra-shallow junction engineering- - Channel and substrate engineering- - Patterning – lithography beyond optics
- 講授:
- 18
Chapter-3
Non-Conventional CMOS Devices 3.1 Vertical structure with multi-gate 3.2 Band structure engineering 3.3 Ultra-thin body and SOI
- 講授:
- 12
Chapter-4
Nano-Si CMOS Device Physics 4.1 Quantum effects 4.2 Threshold voltage modeling 4.3 Mobility modeling 4.4 Subthreshold leakage modeling 4.5 Gate leakage modeling 4.6 Noise modeling
- 講授:
- 6
教師未提供此項資料
Research Journals (IBM, Intel) IEEE Journal on NanotechnologyIEEE Proceedings, TED, EDLIEEE Conferences, IEDM, VLSI, SSDMNanoScience, Science & Nature, etc.
- 地點
- 教師未提供此項資料
- 時間
- Bi-weekly
- 聯絡方式
- adhi.eed07g@nctu.edu.tw
