數位信號處理超大型積體電路
VLSI Digital Signal Processing
| 節 | 週三 |
|---|---|
2 09:00–09:50 | 數位信號處理超大型積體電路 EE112（光復） 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
Digital VLSI design and implementation for various signal processing systems from an architecture point of view.
Signals and Systems Logic Design
無備註
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Homework/Assignments: 40% Midterm: 25% Final: 35%
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| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction to Digital Signal Processing Systems 2/24 |
| 第 2 週 | Iteration Bound 3/3 |
| 第 3 週 | Digital Filters 3/10 |
| 第 4 週 | Pipelined and Parallel Processing 3/17 |
| 第 5 週 | Retiming & Unfolding 3/24 |
| 第 6 週 | Retiming & Unfolding 3/31 |
| 第 7 週 | Folding 4/7 |
| 第 8 週 | Midterm 4/14 |
| 第 9 週 | Folding 4/21 |
| 第 10 週 | Scheduling 4/28 |
| 第 11 週 | Scheduling 5/5 |
| 第 12 週 | CORDIC 5/12 |
| 第 13 週 | Distributed Arithmetic 5/19 |
| 第 14 週 | FFT 5/26 |
| 第 15 週 | Systolic Array 6/2 |
| 第 16 週 | Systolic Array 6/9 |
| 第 17 週 | DSP Processor 6/16 |
| 第 18 週 | Final Exam 6/23 |
1. VLSI Digital Signal Processing Systems: Design and Implementation, Keshab K. Parhi, 1st edition, Wiley-Interscience, 1999. 2. DSP Architecture Design Essentials, Dejan Markovic and Robert W Brodersen, 1st edition, Springer, 2012.
- 地點
- MIRC R301
- 時間
- By appointment
- 聯絡方式
- yck.nctu@gmail.com