數位系統設計(英文授課)
Digital Systems Design
| 節 | 週二 | 週五 |
|---|---|---|
2 09:00–09:50 | 數位系統設計(英文授課) EC016(光復) | |
5 13:20–14:10 | 數位系統設計(英文授課) EC016(光復) 2 節連堂 | |
6 14:20–15:10 |
* 根據陽明交大上課時間表所列
Based on the knowledge of digital circuits, the aims of this course are to explore the principles and design of digital systems and the use of a hardware description language, Verilog, in the design process. Many digital system design examples are included. 本課程以數位電路的知識為基礎,探討數位系統的原理與設計,將硬體描述語言 Verilog 運用在系統設計流程中,並包含許多數位系統設計實例。
Digital Circuit Design ( or Logic Design), Verilog --------------------------------------------------------- 第一週線上討論時間、連結: 9/17 (Fri.) 1:20PM~3:00PM Google meet: https://meet.google.com/vqf-qiso-yai
無備註
Refer to e3 for course related data and information. 課程相關資料與訊息(如:講義、進度、公告等)公佈在網路教學平台 http://e3.nycu.edu.tw 。
(May be adjusted according to the epidemic) Homework/Quizzes: 20%~30% Project: 20%~30% Examinations: 40%~60% Class Participation
Review of Logic Design Fundamentals
Combinational Logic Boolean Algebra Gate-Level Minimization Hazards in Combinational Circuits Latches and Flip-Flops Synchronous Sequential Circuits Sequential Circuit Timing Tristate Logic and Buses
- 講授:
- 3
Introduction to Verilog
Computer-Aided Design Hardware Description Languages Verilog Description of Combinational Circuits Verilog Description of Sequential Circuits Testing a Verilog Model
- 講授:
- 6
- 實作:
- 2
Design Examples
Examples of Combinational Circuits Examples of Sequential Circuits
- 講授:
- 7
- 實作:
- 2
Introduction to Programmable Logic Devices
Brief Overview of Porgrammable Logic Devices Simple Porgrammable Logic Devices (SPLDs) Complex Porgrammable Logic Devices (CPLDs) Field-Programmable Gate Arrays (FPGAs)
- 講授:
- 3
- 其他:
- 2
State Machine Charts and Microprogramming
State Machine Charts Derivation of SM Charts Realization of SM Charts Microprogramming Linked State Machines
- 講授:
- 6
Floating-Point Arithmetic
Representation of Floating-Point Numbers Floating-Point Multiplication Floating-Point Addition Other Floating-Point Operations
- 講授:
- 6
- 實作:
- 2
Additional Topics in Verilog
Verilog Functions Verilog Tasks Multivalued Logic and Signal Resolution Built-in and User-Defined Primitives SRAM Model Named Association Generate Statements System FUnctions Compiler Directives File I/O Functions Timing Checks
- 講授:
- 3
Designing with Field Programmable Gate Arrays
Implementing Functions in FPGAs Shannon's Decomposition Carry Chains and Cascade Chains in FPGAs Dedicated Memory and Multipliers in FPGAs Design Translation (Synthesis) Mapping, Placement, and Routing
- 講授:
- 3
- 其他:
- 2
Design of a RISC Microprocessor
The RISC Philosophy The MIPS ISA MIPS Instruction Encoding Implementation of a MIPS Subset Verilog Model
- 講授:
- 3
Project Presentation
- 講授:
- 3
| 週次 | 主題 |
|---|---|
| 第 1 週 | (線上教學 On-line class) Review of Logic Design Fundamental |
| 第 2 週 | (線上教學 On-line class) Review of Logic Design Fundamental Introduction to Verilog |
| 第 3 週 | (... ...) Introduction to Verilog |
| 第 4 週 | Design Examples |
| 第 5 週 | Design Examples |
| 第 6 週 | Design Examples |
| 第 7 週 | Introduction to Programmable Logic Devices |
| 第 8 週 | Midterm Exam State Machine Charts and Microprogramming |
| 第 9 週 | State Machine Charts and Microprogramming |
| 第 10 週 | State Machine Charts and Microprogramming Floating-Point Arithmetic |
| 第 11 週 | Floating-Point Arithmetic |
| 第 12 週 | Floating-Point Arithmetic Additional Topics in Verilog |
| 第 13 週 | Additional Topics in Verilog |
| 第 14 週 | Designing with Field Programmable Gate Arrays |
| 第 15 週 | Designing with Field Programmable Gate Arrays Project Presentation |
| 第 16 週 | Final Exam Project Presentation |
| 第 17 週 | Flexible learning week: (彈性補充教學) Design of a RISC Microprocessor Project Presentation |
| 第 18 週 | Flexible learning week: (彈性補充教學) Design of a RISC Microprocessor Project Presentation |
References: 1. Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning. 2. M. Morris Mano, Charles R. Kime, and Tom Martin, Logic and Computer Design Fundamentals, 5th Edition, 2016, Pearson Prentice Hall.
- 地點
- EC516
- 時間
- Discuss and decid in class after the semester begins. 開學後,在課堂上討論再定。
- 聯絡方式
- Tel: ext.31832 E-mail: jjshann@cs.nctu.edu.tw
