數位電路設計
Digital Circuit Design
| 節 | 週三 |
|---|---|
3 10:10–11:00 | 數位電路設計 EC016（光復） 2 節連堂 |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
This course is aimed at introducing and demonstrating the fundamental logic design concepts for digital systems.
Not needed.
無備註
Material website: http://viplab.cs.nctu.edu.tw/course/DCD2018_Fall.php
Grading Policy: 1) Quizzes 2) Examinations 每 Participation
Digital Systems and Binary Numbers
1. Digital Systems 2. Binary Numbers 3. Number-Base Conversion 4. Binary Logic
Boolean Algebra and Logic Gates
1. Basic Theorems and Properties of Boolean Algebra 2. Boolean Functions 3. Canonical and Standard Forms 4. Digital Logic Gates
Gate-Level Minimization
1. The Map Method 2. Product of Sums Simplification 3. Don't-Care Conditions 4. NAND and NOR Implementation
Combinational Logic
1. Combinational Circuits 2. Design Procedure 3. Binary Adder-Subtractor / Decimal Adder 4. Binary Multiplier 5. Decoder/Encoder/Multiplexer
Synchronous Sequential Logic
1. Latches 2. Flip-Flops 3. State Reduction and Assignment 4. Design Procedure
Register and Counters
1. Registers 2. Shift Register 3. Ripple Counter 4. Synchronous Counter
Memory and Programmable Logic
1. RAM 2. Memory Decoding 3. Error Detection and Correction 4. ROM 5. Programmable Logic Array 6. Programmable Array Logic
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1. Digital Systems 2. Binary Numbers |
| 第 2 週 | 1. Number-Base Conversion 2. Binary Logic |
| 第 3 週 | 1. Basic Theorems and Properties of Boolean Algebra 2. Boolean Functions |
| 第 4 週 | 1. Canonical and Standard Forms 2. Digital Logic Gates |
| 第 5 週 | 1. The Map Method 2. Product of Sums Simplification |
| 第 6 週 | 1. Don't-Care Conditions 2. NAND and NOR Implementation |
| 第 7 週 | Midterm (I) |
| 第 8 週 | 1. Combinational Circuits 2. Design Procedure 3. Binary Adder-Subtractor / Decimal Adder |
| 第 9 週 | 1. Binary Multiplier 2. Decoder/Encoder/Multiplexer |
| 第 10 週 | 1. Latches 2. Flip-Flops |
| 第 11 週 | 1. State Reduction and Assignment 2. Design Procedure |
| 第 12 週 | Midterm (II) |
| 第 13 週 | 1. Registers 2. Shift Register |
| 第 14 週 | 1. Ripple Counter 2. Synchronous Counter |
| 第 15 週 | 1. RAM 2. Memory Decoding |
| 第 16 週 | 1. Error Detection and Correction 2. ROM |
| 第 17 週 | 1. Programmable Logic Array 2. Programmable Array Logic |
| 第 18 週 | Final Exam |
Text Book: M. Morris Mano and Michael D. Ciletti, "Digital Design", 6th Ed, Prentice Hall, 2019.
- 地點
- EC419R
- 時間
- GH 3:40PM~5:30PM
- 聯絡方式
- 5712121-54815