計算機結構
Computer Architecture
| 節 | 週五 |
|---|---|
2 09:00–09:50 | 計算機結構 ED220（光復） 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
This course aims to provide a strong foundation for students to understand modern computer system architecture and to apply these insights and principles to future computer designs. The course materials focus on advanced topics in computer architecture, fundamentals of quantitative analysis, pipelining, memory hierarchy design, instruction-level and thread-level parallelism, data-level parallelism and graphics processing units, multiprocessors, cache coherence, interconnection networks, multi-core processors and systems-on-chip.
Computer Organization
無備註
Lecture: Chih-Wei Liu 劉志尉 cwliu@twins.ee.nctu.edu.tw 5731685, ED618 Teaching Assistants: 吳宗懋、楊宗燁 54225, ED412 *One semester course, which might include Chapters 1~5, Appendix A~C *http://twins.ee.nctu.edu.tw/
I. Lectures, Homework, and Reading Reports: 15% 1. Adapted from Prof. David Patterson’s class notes 2. Please avoid arriving late or leaving early. 3. At least one problem sets with respect to each lecture 4. Homework should be handed in on time II. Final Project: 15% III. Quizzes: 10% IV. Midterm and Final Exams. 60% (We may have Extra points 5% for some students)
Chap 1: Fundamentals of quantitative design and analysis
The quantitative approach and performance measurement
Appendix A: Instruction set architecture (ISA)
ISA principles and Some ISA examples
Appendix C: Pipelining
The basic and intermediate concepts of 5-stage RISC pipeline architecture
Chap. 2: Memory Hierarchy Design
Cache and memory hierarchies and virtual memory (for multi-processor environment)
Chap. 3: Instruction-Level Parallelism and its Exploitation
1. Compiler techniques for ILP and Branch predictions 2. Dynamic scheduling for ILP 3. Limits on ILP and Multithreading
Chap. 5: Multiprocessors and Thread-Level Parallelism
Models of memory consistency
Chap. 4: Vector processing and Data-Level Parallelism
Vector, SIMD, and GPU architectures
| 週次 | 主題 |
|---|---|
| 第 1 週 | Course Introduction: 1. Technology Trends and Challenges; 2. Historical Perspective |
| 第 2 週 | Performance Metrics: 1. Computer design fundamentals; 2. Principle of quantitative analysis; 3. Instruction set architectures |
| 第 3 週 | Pipelining: 1. review of basic concepts; 2. implementation issues; 3. multi-cycle operations. 4. case study: MIPS R4000. |
| 第 4 週 | Memory-Hierarchy Design: Review of Memmory Hierarchy 1. review of the basics of caches; 2. 6 Basic cache optimization. 3. Virtual Memory 4. Case study. |
| 第 5 週 | Instruction-Level Parallelism: 1. dynamic scheduling; 2. scoreboard, 3. Tomasulo's algorithm. 4. case study |
| 第 6 週 | Instruction-Level Parallelism: 1. branch prediction 2. speculation. 3. Case study |
| 第 7 週 | Instruction-Level Parallelism: 1. compiler techniques. 2. VLIW architectures. |
| 第 8 週 | Thread-Level Parallelism: 1. multithreaded architectures. 2. Case study |
| 第 9 週 | Midterm Exam |
| 第 10 週 | Multi-Core Architectures: 1. chip multi-processors (CMP) and systems-on-chip (SoC). 2. Case study |
| 第 11 週 | Parallel Architectures: 1. taxonomy; types of parallelism; 2. programming and communication models. 3. memory consistency model & cache coherency |
| 第 12 週 | Instruction-Level Parallelism and Its Exploitation: Review Speculation Speculative Tomasulo Example Memory Aliases Exceptions VLIW Advanced Techniques for Instruction Delivery and Speculation Summary |
| 第 13 週 | Limits to ILP (another perspective) Thread Level Parallelism Multithreading Simultaneous Multithreading Power 4 vs. Power 5 Head to Head: VLIW vs. Superscalar vs. SMT Commentary Conclusion |
| 第 14 週 | Multi-Core Architectures: 1. embedded and mobile computing. 2. Case Studies |
| 第 15 週 | Chapter 4 – Multiprocessors and Thread-Level Parallelism Challenges to Parallel Programming Consistency, Coherency, Write Serialization Write Invalidate Protocol Example Conclusion |
| 第 16 週 | Review MP Motivation SISD v. SIMD v. MIMD Centralized vs. Distributed Memory Challenges to Parallel Programming Consistency, Coherency, Write Serialization Write Invalidate Protocol Example Conclusion |
| 第 17 週 | Data-level Parallelism in vector, SIMD, and GPU architectures |
| 第 18 週 | Final Exam. |
John L. Hennessy and David A. Patterson, "Computer Architecture: a Quantitative Approach," 6th Edition, Morgan Kaufmann Publishers, 2019
- 地點
- ED618
- 時間
- 5A or 5X
- 聯絡方式
- 請先用E-mail與老師預約 E-mail: cwliu@twins.ee.nctu.edu.tw TEL: 03-5731685