數位信號處理超大型積體電路
VLSI Digital Signal Processing
| 節 | 週三 |
|---|---|
3 10:10–11:00 | 數位信號處理超大型積體電路 SA321（光復） 3 節連堂 |
4 11:10–12:00 | |
N 12:20–13:10 |
* 根據陽明交大上課時間表所列
Digital VLSI design and implementation for various signal processing systems from an architecture point of view.
Signals and Systems Logic Design
無備註
教師未提供此項資料
Homework/Assignments: 40% Midterm: 25% Final: 35%
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | No Class (NYCU 1st Anniversary ) 2/16 |
| 第 2 週 | Introduction to Digital Signal Processing Systems Iteration Bound 2/23 |
| 第 3 週 | Iteration Bound Digital Filters 3/2 |
| 第 4 週 | Pipelined and Parallel Processing 3/9 |
| 第 5 週 | Retiming & Unfolding 3/16 |
| 第 6 週 | Retiming & Unfolding 3/23 |
| 第 7 週 | Folding 3/30 |
| 第 8 週 | No Class (Holiday) 4/6 |
| 第 9 週 | Midterm 4/13 |
| 第 10 週 | Folding 4/20 |
| 第 11 週 | Scheduling 4/27 |
| 第 12 週 | CORDIC 5/4 |
| 第 13 週 | Distributed Arithmetic 5/11 |
| 第 14 週 | FFT 5/18 |
| 第 15 週 | Systolic Array 5/25 |
| 第 16 週 | Systolic Array 6/1 |
| 第 17 週 | DSP Processor 6/8 |
| 第 18 週 | Final Exam 6/15 |
1. VLSI Digital Signal Processing Systems: Design and Implementation, Keshab K. Parhi, 1st edition, Wiley-Interscience, 1999. 2. DSP Architecture Design Essentials, Dejan Markovic and Robert W Brodersen, 1st edition, Springer, 2012.
- 地點
- MIRC R301
- 時間
- By appointment
- 聯絡方式
- yck.nctu@gmail.com