VLSI數位訊號處理架構設計 (英文授課)

VLSI Digital Signal Processing

學期

110-2

學分

0 學分

當期課號

5264

永久課號

IOC5224

開課單位

資訊科學與工程研究所

授課教師

范倫達

校區

光復

類別

選修

上課時間表

節	週一
A 18:30–19:20	VLSI數位訊號處理架構設計 (英文授課) EC115（光復） 3 節連堂
B 19:30–20:20
C 20:30–21:20

* 根據陽明交大上課時間表所列

概述

Good understanding and design experience of VLSI signal processing algorithms and architecture and chips with applications to DSP and machine learning systems through ASIC-, processor-, and GPU approaches.

先修科目

數位電路設計導論, 訊號與系統

備註

無備註

教學方式

http://viplab.cs.nctu.edu.tw/course/VLSI_DSP2020_Spring.htm Handout is available

評分方式

1. 作業 2. 期中報告 3. 期末計畫

課程大綱

Lecture 1: Introduction to Digital Signal Processing Systems

1.Introduction 2.DSP algorithm
Lecture 1: Introduction to Digital Signal Processing Systems

1.Introduction 2.DSP algorithm
Lecture 2: Iteration Bound

1. Loop Bound and Iteration Bound 2. Compute the Iteration Bound 2.1 Longest Path Matrix Algorithm (LPM) 2.2 Minimum Cycle Mean Method (MCM)
Lecture 2: Iteration Bound

1. Loop Bound and Iteration Bound 2. Compute the Iteration Bound 2.1 Longest Path Matrix Algorithm (LPM) 2.2 Minimum Cycle Mean Method (MCM)
Lecture 3: Pipelining and parallel processing

1. Pipelining of FIR Digital Filter Parallel Processing 2. Pipelining and Parallel Processing for Low Power
Lecture 3: Pipelining and parallel processing

1. Pipelining of FIR Digital Filter Parallel Processing 2. Pipelining and Parallel Processing for Low Power
Lecture 4: Retiming

1. Solving systems of inequelities 2. Retiming technique
Lecture 4: Retiming

1. Solving systems of inequelities 2. Retiming technique
Midterm Report
Lecture 5: Unfolding

2.Critical path, unfolding and retiming 3.Applications of unfolding
Lecture 6: Low-Power CMOS VLSI Design

1. Low power process level design 2. Low power system level design
Lecture 7: FastICA Hardware Architecture for EEG Processing
Lecture 8: Deep Neural Network Hardware Architecture
Lecture 8: Deep Neural Network Hardware Architecture
Lecture 9: Introduction to 3D Graphics Processing Flow Final Project Execution

1. GPU pipeline 1.1 Vertex shader 1.2 Geometry shader 1.2 Fragment shader
Lecture 10: Introduction to modern GPU Hardware

1. History of GPU Hardware 2. GPU Hardware Consideration Modern GPU Hardware Architecture 2.1 NVIDIA GeForce 2.2 AMD (ATI) Radeon 2.3 IMG PowerVR 2.4 ARM Mali
Lecture 11 Geometry Subsystem Design Final Project Execution Final Project Execution

1. Geometry Subsystem 2. Introduction to Shading Algorithms 3. Proposed Low-Complexity Subdivision Algorithm 4. Proposed Power-Area Efficient Geometry Engine 5. Implementation and Comparison Results
Final Project Demo

週次計畫

週次	主題
第 1 週	Lecture 1: Introduction to Digital Signal Processing Systems 3/3
第 2 週	Lecture 1: Introduction to Digital Signal Processing Systems 3/10
第 3 週	Lecture 2: Iteration Bound 3/17
第 4 週	Lecture 2: Iteration Bound 3/24
第 5 週	Lecture 3: Pipelining and parallel processing 3/31
第 6 週	Lecture 3: Pipelining and parallel processing 4/7
第 7 週	Lecture 4: Retiming 4/14
第 8 週	Lecture 4: Retiming 4/21
第 9 週	Midterm Report 4/28
第 10 週	Lecture 5: Unfolding 5/5
第 11 週	Lecture 6: Low-Power CMOS VLSI Design 5/12
第 12 週	Lecture 7: FastICA Hardware Architecture for EEG Processing 5/19
第 13 週	Lecture 8: Deep Neural Network Hardware Architecture 5/26
第 14 週	Lecture 8: Deep Neural Network Hardware Architecture Final Project Planning 6/2
第 15 週	Lecture 9: Introduction to 3D Graphics Processing Flow Final Project Execution 6/9
第 16 週	Lecture 10: Introduction to modern GPU Hardware Final Project Execution 6/16
第 17 週	Lecture 11: Geometry Subsystem Design Final Project Execution 6/23
第 18 週	Final Project Demo 6/30

教科書

K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. NY: Wiley, 1999. Reference Books: P. Pirsch, Architectures for Digital Signal Processing. NY: Wiley, 1998. ※請修課同學尊重智慧財產權!勿隨意過度影印教科書或使用未經授權之著作權與電腦軟體等。

Office Hours

地點: EC-419R
時間: Tuesday: GH
聯絡方式: ext 54815