超大型積體電路系統設計

VLSI System Design and Application

學期

111-1

學分

0 學分

當期課號

535308

永久課號

EECN30193

開課單位

電控工程研究所

授課教師

趙昌博

校區

光復

類別

選修

上課時間表

節	週二
5 13:20–14:10	超大型積體電路系統設計 EE623（光復） 3 節連堂
6 14:20–15:10
7 15:30–16:20

* 根據陽明交大上課時間表所列

概述

To establish students fundamental knowledge and skill on VLSI.

先修科目

Microelectronics, Logic Design

備註

無備註

教學方式

There will be TAs responsible for grading homeworks/exams and guiding students to do projects.

評分方式

7-10 HWs, 45%. Midterm and Final, 45% Term project 20%

課程大綱

Course Introduction

講授：

4
CMOS Logics and Fabrication

講授：

3
Introduction to VLSI Design

講授：

3
Fundamental electrical characteristics of MOS devices and nonlinearities

講授：

6
MOS Device Performance Evaluation

講授：

4
Power Consumption of CMOS Circuits

講授：

3
Continued Power Issues of MOS Device

講授：

3
CMOS Chip Wiring Design

講授：

3
CMOS Circuit Modeling

講授：

4
CMOS Gates and Sequential Design

講授：

6
Datapath Design

講授：

6
Memories

講授：

6

週次計畫

週次	主題
第 1 週	Course Introduction 9/14
第 2 週	CMOS Logics nand Fabrication Introduction to VLSI Design 9/21
第 3 週	Mos transistor theory Fundamental electrical characteristics of MOS devices and nonlinearities 9/28
第 4 週	Mos transistor theory Fundamental electrical characteristics of MOS devices and nonlinearities 10/5
第 5 週	Delay - Logical effort, RC Delay model 10/12
第 6 週	Delay - Logical effort, RC Delay model Power - Consumption of CMOS Circuits, Energy-Delay Optimization 10/19
第 7 週	Power - Consumption of CMOS Circuits, Energy-Delay Optimization Power management 10/26
第 8 週	Midterm Exam 11/02
第 9 週	Combinational Circuit Design 11/09
第 10 週	Combinational Circuit Design CMOS Gates and Sequential Design 11/16
第 11 週	Continued on Sequential Design 11/23
第 12 週	Interconnect - CMOS Chip Wiring Design 11/30
第 13 週	Datapath Design 12/07
第 14 週	Datapath Design 12/14
第 15 週	SRAM 12/21
第 16 週	SRAM 12/28
第 17 週	Final exam 1/04
第 18 週	1/11

教科書

N. H. E. Weste and David M. Harris, "Integrated Circuit Design," Fourth Edition, Pearson Education Inc., Addison-Wesley, 2011. Sung-Mo Kang, CMOS Digital Integrated Circuits: Analysis and Design, 4/e

Office Hours

地點: EE Room. 735
時間: 16:30 - 18:20, every Wed.
聯絡方式: (03)5131377, 校內分機