類比混合訊號電路設計特論
Special topics in analog mixed-signal circuit design
| 節 | 週五 |
|---|---|
6 14:20–15:10 | 類比混合訊號電路設計特論 EDB27（光復） 3 節連堂 |
7 15:30–16:20 | |
8 16:30–17:20 |
* 根據陽明交大上課時間表所列
This course will introduce the fundamentals of different kinds of ADC/Wireline architectures. The content will include the ADC/Wireline building blocks and their non-idealities in practical circuits. Students need to select one of the ADC/Wireline architectures and practice the design flow from Matlab modeling, circuit simulation with ideal blocks, and then replace part of the blocks with real circuits.
Microelectronics, Circuit theories, Introduction to analog integrated circuits
無備註
Reference : 1. Behzad Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, 1994. 2. Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”OXFORD, 2012, 3rd-Edition
Midterm exam 25%, Final exam 25%, Homework 25%, Final project 25%
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| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction of this course (content & rating rules) Introduction of ADC 9/16 |
| 第 2 週 | ADC architectures and tradeoffs |
| 第 3 週 | SAR ADC and comparator |
| 第 4 週 | Pipeline ADC and amplifier |
| 第 5 週 | Noise-shaping ADC and loop filter |
| 第 6 週 | DAC mismatch calibration and shaping |
| 第 7 週 | Midterm exam (ADC) |
| 第 8 週 | High-Speed Links Overview -SerDes standards and link sequence -Noise and signaling PI/SI and noise budget -Channels, transmission lines and termination |
| 第 9 週 | High-Speed Links Circuits and Systems Receiver circuits: AFE, DFE, adaptive algorithm |
| 第 10 週 | High-Speed Links Circuits and Systems Receiver circuits: CDR, De-Multiplexer |
| 第 11 週 | High-Speed Links Circuits and Systems Transmitter circuits: Driver, Multiplexer, FIR EQ |
| 第 12 週 | Phase-Locked Loop (PLL) Introduction of PLL Building Blocks in PLL |
| 第 13 週 | Phase-Locked Loop (PLL) Phase noise and jitter PLL Implementation and Simulation |
| 第 14 週 | Final project report (ADC) |
| 第 15 週 | Final project report (High-Speed Links/PLL) |
| 第 16 週 | Final exam (High-Speed Links/PLL) |
Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001.
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