數位電路設計
Digital Circuit Design
| 節 | 週三 |
|---|---|
3 10:10–11:00 | 數位電路設計 EC122（光復） 2 節連堂 |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
This course is aimed at introducing the fundamental concepts and methods and the basic tools used in the logic design of digital circuits. (本課程主要介紹數位電路中邏輯設計的重要觀念與方法及基本工具)
教師未提供此項資料
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Refer to https://e3.nycu.edu.tw for the related data and information, e.g.s, slides, schedule, announcements, etc, of the course. 課程相關資料與訊息(如:講義、進度、公告等)公佈在網路教學平台 http://e3.nycu.edu.tw
Exams: 60-80% (3 exams) Quizzes/Homework/Implementation/Participation: 20-40%
Digital Systems and Binary Numbers
Digital Systems Binary, Octal, and Hexadecimal Numbers Signed Binary Numbers Binary Codes Binary Logic
- 講授：
- 3
- 示範：
- 1
Boolean Algebra and Logic Gates
Boolean Algebra Boolean Functions Canonical and Standard Forms Digital Logic Gates
- 講授：
- 4
- 示範：
- 2
Gate-Level Minimization
The Map Method Don’t-Care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language
- 講授：
- 5
- 示範：
- 2
- 其他：
- 2, Exam of Unit 1~3
Combinational Logic
Combinational Circuits Analysis Procedure of Combinational Circuits Design Procedure of Combinational Circuits Arithmetic Functions and Circuits: Binary Adder-Subtractor, Decimal Adder, Binary Multiplier, Magnitude Comparator Combinational Functions and Circuits: Decoders, Encoders, Multiplexers HDL Models of Combinational Circuits
- 講授：
- 6
- 示範：
- 2
Synchronous Sequential Logic
Sequential Circuits Storage Elements: Latches, Flip-Flops Analysis Procedure of Clocked Sequential Circuits Design Procedure of Clocked Sequential Circuits HDL Models of Sequential Circuits
- 講授：
- 7
- 示範：
- 3
- 其他：
- 2, Exam of Unit 4~5
Registers ad Counters
Registers and Shift Registers Ripple Counters and Synchronous Counters Other Counters HDL for Registers and Counters
- 講授：
- 5
- 示範：
- 1
Memory and Programmable Logic
Random-Access Memory Read-Only Memory Programmable Logic Array Programmable Array Logic Sequential Programmable Devices
- 講授：
- 5
- 示範：
- 1
- 其他：
- 2, Exam of Unit 6~7
| 週次 | 主題 |
|---|---|
| 第 1 週 | SyllabusChapter 1 Digital Systems and Binary Numbers 2023-02-15(三) |
| 第 2 週 | Chapter 1 Digital Systems and Binary NumbersChapter 2 Boolean Algebra and Logic Gates 2023-02-22(三) |
| 第 3 週 | Chapter 2 Boolean Algebra and Logic Gates 2023-03-01(三) |
| 第 4 週 | Chapter 2 Boolean Algebra and Logic GatesChapter 3 Gate-Level Minimization 2023-03-08(三) |
| 第 5 週 | Chapter 3 Gate-Level Minimization 2023-03-15(三) |
| 第 6 週 | Chapter 3 Gate-Level MinimizationExam#1 2023-03-22(三) |
| 第 7 週 | Chapter 4 Combinational Logic 2023-03-29(三) |
| 第 8 週 | Chapter 4 Combinational Logic 2023-04-05(三) |
| 第 9 週 | Chapter 4 Combinational Logic 2023-04-12(三) |
| 第 10 週 | Chapter 5 Synchronous Sequential Logic 2023-04-19(三) |
| 第 11 週 | Chapter 5 Synchronous Sequential LogicExam#2 2023-04-26(三) |
| 第 12 週 | Chapter 5 Synchronous Sequential Logic 2023-05-03(三) |
| 第 13 週 | Chapter 6 Registers ad Counters 2023-05-10(三) |
| 第 14 週 | Chapter 6 Registers ad Counters 2023-05-17(三) |
| 第 15 週 | Chapter 7 Memory and Programmable Logic 2023-05-24(三) |
| 第 16 週 | Exam#3 2023-05-31(三) |
| 第 17 週 | Flexible Learning Week (彈性補充教學) 2023-06-07(三) |
| 第 18 週 | Flexible Learning Week (彈性補充教學) 2023-06-14(三) |
M. Morris Mano and Michael D. Ciletti, Digital Design, 6th ed. (2019), Prentice Hall.
- 地點
- EC516
- 時間
- TBD (開學後討論再定)
- 聯絡方式
- ext. 31832 jjshann@cs.nctu.edu.tw