數位電路與系統
Digital Circuits and Systems
| 節 | 週二 | 週四 |
|---|---|---|
7 15:30–16:20 | 數位電路與系統 ED219（光復） 2 節連堂 | |
8 16:30–17:20 | 數位電路與系統 ED219（光復） |
* 根據陽明交大上課時間表所列
This course is intended to teach undergraduate students to understand and design digital systems. The course contents cover those skills needed for current industrial digital system design using Verilog-HDL and modern CAD tools. Particular attention is paid to system level issues including factoring and partitioning digital systems, interface design, and interface timing. Topics needed for a deep understanding of digital circuits, such as timing analysis, metastability, and synchronization, will also be covered. Upon completion of this-semester course, students should be well-prepared to practice digital design in industry. They will have all of the tools they need for contemporary practice. And the experience will come with time. 本課程不但教你用Verilog ,讓你會做IC設計,還教你什麼是好的IC設計。 今年課程有要求gate level simulation,與FPGA lab。 沒修過logic design,請勿修課,如需修課,請先自修邏輯設計 (建議3小時快速入門 https://ppt.cc/fmY2yx,整學期課程 https://ppt.cc/fNbCGx)。(如需書,建議參考以下Mano書),具備將問題轉成logic equation/FSM 的能力,與簡單化簡能力。 **************************************************************************** 教室空間有限,課程上限一旦額滿,不開放加簽。所有選課請透過選課系統。 **************************************************************************** 2023 Spring course recording (Lecture only) https://www.youtube.com/playlist?list=PLCUEmRsKEgZ4p8HK5IXMrohliNuRttqpt ****************************************************************************
logic design
無備註
1. All materials will be available on NYCU new e3 web site. e3.nycu.edu.tw 2. 如因疫情,請依公告,進行遠端上課。實作課遠端連線,TA線上接受提問(週四上課時間)。 3. Lecture 部分會有上課錄影 (https://ppt.cc/fzrV1x),請課後自行觀看,不另行通知。 4. 配合疫情,若遠端上課,學校要求每堂課要點名,請配合連上e3.nycu.edu.tw 點名系統。 5. 第三周後週四為上機實驗課(依公告),週二為lecture 課程 6. 本門課因空間因素,不接受手動加簽,請直接在線上選課,不接受超過上限人數。上限人數有可能因空間關係隨時做調整。請自行注意。 7. 開放旁聽,請寄學號姓名給教授
Exams: one final exam (25%) (Closed book) 實作課 mini-online lab and test (10%) 每周四下午第8節,於ED415/ED417 (except the first two week) 1 HWs on combinational logic , 4 HWs on sequential logic on Verilog-HDL and FPGA (24%, each 5 points, first homework 4%), one online test (10% ) final-project (20%), 1st demo (original score), 2nd demo (0.7x), third demo (optional, 0.5x),請討論勿抄襲,抄襲比對確認者 0 分。 short midterm test (8%) (closed book)。classroom participation (3%)
Verilog
Combinational logic
Verilog
Sequential logic/FSM
Testbench design
timing control and file I/O
Coding style and Verification
Good programming guide
Single cycle MIPS
Example
Pipeline architecture
architecture design example
Timing and synthesis
timing analysis and synthesis
| 週次 | 主題 |
|---|---|
| 第 1 週 | introduction 2024-02-20(二),2024-02-22(四) |
| 第 2 週 | Verilog overview 2024-02-27(二),2024-02-29(四) |
| 第 3 週 | Verilog overview 2024-03-05(二),2024-03-07(四) |
| 第 4 週 | modeling combinational logic 2024-03-12(二),2024-03-14(四) |
| 第 5 週 | model sequential logic 2024-03-19(二),2024-03-21(四) |
| 第 6 週 | testbench programming 2024-03-26(二),2024-03-28(四) |
| 第 7 週 | arithmetic 4/4 Holiday 2024-04-02(二),2024-04-04(四) |
| 第 8 週 | model datapath FSM 4/11 Short midterm test 2024-04-09(二),2024-04-11(四) |
| 第 9 週 | factor FSM 2024-04-16(二),2024-04-18(四) |
| 第 10 週 | microcode 2024-04-23(二),2024-04-25(四) |
| 第 11 週 | pipeline 2024-04-30(二),2024-05-02(四) |
| 第 12 週 | timing/metastability 2024-05-07(二),2024-05-09(四) |
| 第 13 週 | system level design 2024-05-14(二),2024-05-16(四) |
| 第 14 週 | Verification and testing 2024-05-21(二),2024-05-23(四) |
| 第 15 週 | 5/28 Final exam 2024-05-28(二),2024-05-30(四) |
| 第 16 週 | 6/4 On-line test (from 3:30 AM to 6:20PM) 2024-06-04(二),2024-06-06(四) |
Textbook. Digital Design: a systems approach by William J. Dally and R. Curtis Harting Cambridge, University Press Reference book: 1. Introduction to Logic Circuits & Logic Design with Verilog, by Brock J. LaMeres, Springer 2. Verilog HDL Primer 3. Digital Design: With an Introduction to the Verilog HDL, By M. Morris R. Mano and Michael D. Ciletti
- 地點
- ED406
- 時間
- 2 EF, please make an appointment in advance.
- 聯絡方式
- TEL: 54243 e-mail: tschang@nycu.edu.tw