邏輯設計
Logic Design
| 節 | 週二 | 週五 |
|---|---|---|
5 13:20–14:10 | 邏輯設計 ED219（光復） 2 節連堂 | |
6 14:20–15:10 | ||
7 15:30–16:20 | 邏輯設計 ED219（光復） |
* 根據陽明交大上課時間表所列
This course represents the introductory engineering course in the fields of electrical engineering and computer science. It lays the foundational groundwork, encompassing the essential theorems and operations of Boolean algebra, as well as the design of digital circuits. Students will develop their logical thinking skills and engage in the design of digital logic circuits and systems.
Basic English Reading
無備註
Lecture with PPT as class note. E3 online system 本年度以實體上課為主,若因各種突發狀況需線上,將另外公告於E3.
1. Examination I: 25% 2. Examination II: 25% 3. Homeworks: 15% 4. Final Examination: 35% 5. Verilog Homework: 5% (Optional) The final exam will be held in week #17.
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | Course introduction, Number System and Conversion 2024-02-20(二),2024-02-23(五) |
| 第 2 週 | Boolean Algebra 2024-02-27(二),2024-03-01(五) |
| 第 3 週 | Algebraic Simplification 2024-03-05(二),2024-03-08(五) |
| 第 4 週 | Applications of Boolean Algebra 2024-03-12(二),2024-03-15(五) |
| 第 5 週 | Karnaugh Maps (Unit 5) 2024-03-19(二),2024-03-22(五) |
| 第 6 週 | Study Break (Optional), Midterm Examination I 2024-03-26(二),2024-03-29(五) |
| 第 7 週 | Multi-Level Gate Networks NAND and NOR Gates 2024-04-02(二),2024-04-05(五) |
| 第 8 週 | Combinational Circuits Design and Simulation Using Gates 2024-04-09(二),2024-04-12(五) |
| 第 9 週 | Multiplexers, Decoders, Read-Only Memories, and Programmable Logic Devices 2024-04-16(二),2024-04-19(五) |
| 第 10 週 | Latches and Flip-Flops 2024-04-23(二),2024-04-26(五) |
| 第 11 週 | Registers and Counters (Unit 12) 2024-04-30(二),2024-05-03(五) |
| 第 12 週 | Study Break (Optional), Midterm Examination II 2024-05-07(二),2024-05-10(五) |
| 第 13 週 | Analysis of Clocked Sequential Networks 2024-05-14(二),2024-05-17(五) |
| 第 14 週 | Derivation of State Graphs and Tables 2024-05-21(二),2024-05-24(五) |
| 第 15 週 | Reduction of State Tables/State Assignment 2024-05-28(二),2024-05-31(五) |
| 第 16 週 | Sequential Circuit Design 2024-06-04(二),2024-06-07(五) |
Fundamental of Logic Design, 7th Edition, Charles H. Roth, Jr., Larry L. Kinney, CENGAGE Learning, 2014 代理商: 滄海書局 TEL: (04) 2708-8787, FAX: (04) 2708-7799
- 地點
- ED403
- 時間
- E-mail first to make an appointment.
- 聯絡方式
- yicwu@nycu.edu.tw