計算機組織
Computer Organization
| 節 | 週四 |
|---|---|
5 13:20–14:10 | 計算機組織 EC022（光復） 2 節連堂 |
6 14:20–15:10 |
* 根據陽明交大上課時間表所列
This course aims to introduce the computer organization that includes CPU, memory, and cache. The Intended Lecture Outcomes (ILOs) is shown below. 1. Learn the great ideas of computer design and implementation 2. Learn the design and formats of RISC-V instruction set 3. Understand the detail of the pipelining CPU processor organization 4. Introduce the memory hierarchies (DRAM and Cache) 5. Implement a simple RISC-V CPU architecture
C programming, digital system design, and verilog programming
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5 labs (60 %) 2 exams (40 %) Lab 0 Environment Setup & simple verilog practice Lab 1 Single Cycle CPU w/ Simple RISC-V Instruction Lab 2 Single Cycle CPU w/ Branch Instruction Lab 3 Pipelining CPU Lab 4 Data/Control Hazard Lab 5 Implement Cache Simulator
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| 週次 | 主題 |
|---|---|
| 第 1 週 | Technology Trends and Quantitative Analaysis for Performance 2024-02-22(四) |
| 第 2 週 | RISC-V Instructions Sets, Part 1 2024-02-29(四) |
| 第 3 週 | RISC-V Instructions Sets, Part 2 2024-03-07(四) |
| 第 4 週 | RISC-V Instructions Sets, Part 3 2024-03-14(四) |
| 第 5 週 | Arithmetic for Computers 2024-03-21(四) |
| 第 6 週 | RISC-V Single-Cycle Implementation 2024-03-28(四) |
| 第 7 週 | RISC-V Single-Cycle Implementation 2024-04-04(四) |
| 第 8 週 | Pipeline and Hazards 2024-04-11(四) |
| 第 9 週 | Pipeline and Hazards 2024-04-18(四) |
| 第 10 週 | Midterm 2024-04-25(四) |
| 第 11 週 | Branch Predictor 2024-05-02(四) |
| 第 12 週 | Memory Hierarchy - DRAM 2024-05-09(四) |
| 第 13 週 | Memory Hierarchy - Cache Organization 2024-05-16(四) |
| 第 14 週 | Memory Hierarchy - Cache Optimization 2024-05-23(四) |
| 第 15 週 | Data-Level Parallelism 2024-05-30(四) |
| 第 16 週 | Thread-Level Parallelism 2024-06-06(四) |
David A. Patterson, John L. Hennessy, Computer Organization and Design RISC-V Edition: The Hardware Software Interface, Morgan Kaufmann, 5e
- 地點
- EC707
- 時間
- 4CD
- 聯絡方式
- ttyeh@cs.nycu.edu.tw