數位電路設計
Digital Circuit Design
| 節 | 週三 | 週五 |
|---|---|---|
3 10:10–11:00 | 數位電路設計 ED117（光復） 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 數位電路設計 ED117（光復） |
* 根據陽明交大上課時間表所列
This course is aimed at introducing and demonstrating the fundamental logic design concepts for digital systems.
Not needed.
無備註
http://viplab.cs.nycu.edu.tw/course/DCD2025_Spring.php
Grading Policy: 1) Quizzes 2) Examinations 3) Participation
Digital Systems and Binary Numbers
1. Digital Systems 2. Binary Numbers 3. Number-Base Conversion 4. Binary Logic
Boolean Algebra and Logic Gates
1. Basic Theorems and Properties of Boolean Algebra 2. Boolean Functions 3. Canonical and Standard Forms 4. Digital Logic Gates
Gate-Level Minimization
1. The Map Method 2. Product of Sums Simplification 3. Don't-Care Conditions 4. NAND and NOR Implementation 5. Other Two-level Implementation
Combinational Logic
1. Combinational Circuits 2. Design Procedure 3. Binary Adder-Subtractor / Decimal Adder 4. Binary Multiplier 5. Decoder/Encoder/Multiplexer
Synchronous Sequential Logic
1. Latches 2. Flip-Flops 3. State Reduction and Assignment 4. Design Procedure
Register and Counters
1. Registers 2. Shift Register 3. Ripple Counter 4. Synchronous Counter
Memory and Programmable Logic
1. RAM 2. Memory Decoding 3. Error Detection and Correction 4. ROM 5. Programmable Logic Array 6. Programmable Array Logic
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1. Digital Systems 2. Binary Numbers 2025-02-19(三),2025-02-21(五) |
| 第 2 週 | 1. Number-Base Conversion 2. Binary Logic 2025-02-26(三),2025-02-28(五) |
| 第 3 週 | 1. Basic Theorems and Properties of Boolean Algebra 2. Boolean Functions 3. Canonical and Standard Forms 4. Digital Logic Gates 2025-03-05(三),2025-03-07(五) |
| 第 4 週 | 1. The K-Map Method 2. Product of Sums Simplification 2025-03-12(三),2025-03-14(五) |
| 第 5 週 | 1. Don't-Care Conditions 2. NAND and NOR Implementation 3. Other Two-level Implementation 2025-03-19(三),2025-03-21(五) |
| 第 6 週 | 1. Combinational Circuits 2. Design Procedure 2025-03-26(三),2025-03-28(五) |
| 第 7 週 | 1. Binary Adder-Subtractor/Decimal Adder 2. Binary Multiplier 3. Decoder/Encoder/Multiplexer 2025-04-02(三),2025-04-04(五) |
| 第 8 週 | 1. Latches 2. Flip-Flops 2025-04-09(三),2025-04-11(五) |
| 第 9 週 | 1. State Reduction and Assignment 2. Design Procedure 2025-04-16(三),2025-04-18(五) |
| 第 10 週 | Midterm 2025-04-23(三),2025-04-25(五) |
| 第 11 週 | 1. Registers 2. Shift Register 2025-04-30(三),2025-05-02(五) |
| 第 12 週 | 1. Ripple Counter 2. Synchronous Counter 2025-05-07(三),2025-05-09(五) |
| 第 13 週 | 1. RAM 2. Memory Decoding 3. Error Detection and Correction 2025-05-14(三),2025-05-16(五) |
| 第 14 週 | 1. ROM 2. Programmable Logic Array 3. Programmable Array Logic 2025-05-21(三),2025-05-23(五) |
| 第 15 週 | Content Review 2025-05-28(三),2025-05-30(五) |
| 第 16 週 | Final Exam 2025-06-04(三),2025-06-06(五) |
Text Book: M. Morris Mano and Michael D. Ciletti, "Digital Design", 6th Ed, Prentice Hall, 2019.
- 地點
- EC419R
- 時間
- Wednesday 8AM~10AM
- 聯絡方式
- 5712121-54815