邏輯設計
Logic Design
| 節 | 週二 | 週五 |
|---|---|---|
3 10:10–11:00 | 邏輯設計 ED220（光復） 2 節連堂 | |
4 11:10–12:00 | ||
5 13:20–14:10 | 邏輯設計 ED220（光復） |
* 根據陽明交大上課時間表所列
This is the most fundamental course in Digital Electronics and Computer design and is the first engineering course of electronics, electrical and computer area of NYCU. You will first learn basic theorems and operations of Boolean algebra: A way to train your logic thinking capability. You will design digital logic circuits and systems and know there are several kinds of solutions for different applications. This is an interesting course that you will have home works and projects of real stuff. ※本課程將培育學生具備下述幾項核心能力: 1.2 電子、資訊領域相關專業知識與能力 1.3 電子、資訊領域之實作技術,並具有發掘、分析、解決問題及創新的能力 3.2 具有通過全民英檢中高級初試之能力 ※本課程將培育學生具備下述幾項基本素養: 1 養成學生具備電子工程基礎與專業知識,並配合實作,達到理論與實務相結合之目的。使學生具備推論、分析、創新及整合能力。
Shall have essential ability of English reading.
無備註
Lecture with power point file E3 on line system
Home Works Examination (In-Class) 20% Midterm Examination 30% Mini-Project (Verilog) 20% Final Examination 30%
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1.Number System and Conversion 2025-09-02(二),2025-09-05(五) |
| 第 2 週 | 2.Boolean Algebra 2025-09-09(二),2025-09-12(五) |
| 第 3 週 | 3.Algebraic Simplification 2025-09-16(二),2025-09-19(五) |
| 第 4 週 | 4.Applications of Boolean Algebra 2025-09-23(二),2025-09-26(五) |
| 第 5 週 | 5.Karnaugh Maps 2025-09-30(二),2025-10-03(五) |
| 第 6 週 | 6.Multi-Level Gate Networks NAND and NOR Gates 2025-10-07(二),2025-10-10(五) |
| 第 7 週 | 7.Combinational Circuits Design and Simulation Using Gates 2025-10-14(二),2025-10-17(五) |
| 第 8 週 | 8. Midterm examination 2025-10-21(二),2025-10-24(五) |
| 第 9 週 | 9.Multiplexers, Decoders, Read-Only Memories, and Programmable Logic Devices 2025-10-28(二),2025-10-31(五) |
| 第 10 週 | 10.Introduction of Hardware Description Language: Verilog11. Latches and Flip-Flops 2025-11-04(二),2025-11-07(五) |
| 第 11 週 | 11.Registers and Counters 2025-11-11(二),2025-11-14(五) |
| 第 12 週 | 12. Analysis of Clocked Sequential Networks 2025-11-18(二),2025-11-21(五) |
| 第 13 週 | 13.Derivation of State Graphs and Tables 2025-11-25(二),2025-11-28(五) |
| 第 14 週 | 14.Reduction of State Tables/State Assignment16. Sequential Circuit Design 2025-12-02(二),2025-12-05(五) |
| 第 15 週 | Sequential Circuit Design 2025-12-09(二),2025-12-12(五) |
| 第 16 週 | Final Examination 2025-12-16(二),2025-12-19(五) |
Fundamental of Logic Design, 7th Edition, Charles H. Roth, Cenegage Learing, 2014
- 地點
- ED619; ext. 31475
- 時間
- Tuesday 12:10-13:00
- 聯絡方式
- By email: jerryjou@nycu.edu.tw