實體設計自動化
Physical Design Automation
| 節 | 週二 |
|---|---|
9 17:30–18:20 | 實體設計自動化 ED116(光復) 3 節連堂 |
A 18:30–19:20 | |
B 19:30–20:20 |
* 根據陽明交大上課時間表所列
This course introduces the principles, algorithms, and practical tools used in VLSI physical design automation, a critical stage of modern integrated circuit (IC) design. The course focuses on transforming a synthesized gate-level netlist into a manufacturable physical layout while meeting performance, power, and area constraints. Key topics include partitioning, floorplanning, placement, clock tree synthesis, routing, design for manufacturability (DFM), and 3D IC integration, with emphasis on optimization techniques and algorithmic foundations. Students will study timing closure, power integrity, signal integrity, and variability-aware design in advanced technology nodes.
C / C++ / Python Programming Data structures Algorithms Logic design (nice to have) VLSI design (nice to have)
無備註
Algorithms for VLSI Physical Design Automation, 3/e (Hardcover) https://nycu.primo.exlibrisgroup.com/permalink/886UST_NYCU/564rer/alma990001001020206772 VLSI Physical Design: From Graph Partitioning to Timing Closure https://nycu.primo.exlibrisgroup.com/permalink/886UST_NYCU/cqntog/cdi_askewsholts_vlebooks_9783030964153
Programming Assignments (60%) Midterm (20%) Final Exam (20%)
Complexities & Algorithms
Analysis of computational complexity in physical design problems and introduction to key algorithmic techniques such as heuristics, approximation algorithms, and optimization methods.
Partitioning
Techniques for dividing large circuits into smaller, manageable blocks to improve scalability, reduce interconnect cost, and enable hierarchical design.
Floorplanning
Methods for determining the size, shape, and relative placement of major circuit blocks while optimizing area, aspect ratio, and interconnect performance.
Placement
Algorithms for assigning exact locations to standard cells to minimize wirelength, congestion, and timing violations under physical and design constraints.
Routing
Global and detailed routing techniques that establish signal connections, clock tree, and power network, while satisfying design rules, timing requirements, and signal integrity constraints.
DFM and 3D IC
Design for Manufacturability concepts addressing yield, variability, and lithography effects, along with physical design challenges and opportunities in 3D integrated circuits and advanced packaging.
Introduction
Overview of the VLSI physical design flow, design objectives (power, performance, area), technology constraints, and the role of automation in modern IC design.
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction |
| 第 2 週 | Complexities & Algorithms |
| 第 3 週 | Partitioning |
| 第 4 週 | Partitioning |
| 第 5 週 | Floorplanning |
| 第 6 週 | Floorplanning |
| 第 7 週 | Floorplanning |
| 第 8 週 | Midterm |
| 第 9 週 | Placement |
| 第 10 週 | Placement |
| 第 11 週 | Placement |
| 第 12 週 | Routing |
| 第 13 週 | Routing |
| 第 14 週 | Routing |
| 第 15 週 | DFM & 3D IC |
| 第 16 週 | Final Exam |
Reference books: S. H. Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons, 1999 L.-T. Wang, Y.-W. Chang, and K.-T. Cheng, Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon), Morgan Kaufmann, 2009. L. Lavagno, I. Markov, and G. Martin, L. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, CRC, 2nd Ed., 2016. Sait and Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Co., 1999
- 地點
- EF369
- 時間
- By appointment
- 聯絡方式
- mphlin@nycu.edu.tw
