前瞻CMOS製程整合工程
Advanced CMOS Process Integration Engineering
| 節 | 週五 |
|---|---|
5 13:20–14:10 | 前瞻CMOS製程整合工程 A305（光復） 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
A qualified process integration engineer requires to possess interdisciplinary knowledge across advanced CMOS device physics, semiconductor fabrication process, and basic CMOS device/standard cell/SRAM designs. Yield enhancement and reliability qualification are also important functional areas. The goal of this course is to provide the comprehensive and practical approaches to introduce the aforementioned subjects with sufficient depth for students interested in the process integration engineering (PIE) by lecturers from industry.
Semiconductor Device and Physics (Required); Basic knowledge in CMOS circuits (Preferred)
無備註
上課為保障智慧財產權，不得照相、錄音或錄影。
Mid-Term Exam 50% Final Exam 50%
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| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction (Holiady, On-Line) 2026-02-27(五) |
| 第 2 週 | Evolution of CMOS devices 2026-03-06(五) |
| 第 3 週 | Fundamental Process Introduction 2026-03-13(五) |
| 第 4 週 | Gate, Standard cells and SRAM Cells 2026-03-20(五) |
| 第 5 週 | Device Engineering 2026-03-27(五) |
| 第 6 週 | Fabrication processes of advanced CMOS (I)-FEOL (Holiday, On-Line) 2026-04-03(五) |
| 第 7 週 | Device Engineering 2026-04-10(五) |
| 第 8 週 | Mid-term 2026-04-17(五) |
| 第 9 週 | Device Engineering 2026-04-24(五) |
| 第 10 週 | Fabrication processes of advanced CMOS (II)- MEOL/BEOL (Holiday, On-Line) 2026-05-01(五) |
| 第 11 週 | Device Engineering 2026-05-08(五) |
| 第 12 週 | Lithography/Patterning 2026-05-15(五) |
| 第 13 週 | Lithography/Patterning Technology 2026-05-22(五) |
| 第 14 週 | Yield Enhancement & Process Defects 2026-05-29(五) |
| 第 15 週 | Product Development Cycle: Ultra Low Power Technology 2026-06-05(五) |
| 第 16 週 | Final Exam 2026-06-12(五) |
課程講義
- 地點
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- 時間
- By appointment
- 聯絡方式
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