超大型積體電路系統設計
VLSI System Design and Application
| 節 | 週四 |
|---|---|
5 13:20–14:10 | 超大型積體電路系統設計 EE102（光復） 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
Digital integrated circuit design fundamentals. Design specifications: functionality, performance, reliability, manufacturability, testability, cost. Standards, silicon compilers, foundries. Design layout rules, rule checking. Circuit extraction, simulation, verification.
introduction to VLSI Logic Design Electronics I and II Hspice, verilog, Cadence
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40% 2 Midterm Exams 35% Homework 5% Participation (attendance, quizzes, etc.) 20% Final Project ( Presentation 10%, Project Report 10%) Students are encouraged to participate in class. All homework assignments will be assigned and submitted via the New E3. The submitted homework must be in pdf format. Example: (studene ID number)_HW(homework number).pdf114511004_HW2.pdf NOTE: Cheating at any time in this course will cause you to fail the course. This includes copying homework, copying circuit design files, copying from AI, cheating on exams, or any other form of unethical behavior.
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| 週次 | 主題 |
|---|---|
| 第 1 週 | I |
| 第 2 週 | CMOS circuit |
| 第 3 週 | Combinational circuit design |
| 第 4 週 | sequential circuit design |
| 第 5 週 | sequential circuit design Adder_Mutiplier_ALU |
| 第 6 週 | Adder_Mutiplier_ALU RAM_ROM |
| 第 7 週 | Clocking of Synchronous Circuits Asynchronous Data Acquisition |
| 第 8 週 | Midterm exam I. |
| 第 9 週 | Gate- and Transister-level Deign Power efficiency and heat removal |
| 第 10 週 | Power efficiency and heat removal Signal integrity |
| 第 11 週 | Midterm exam II |
| 第 12 週 | Validatiton and Testing |
| 第 13 週 | Final Project:Neural-network/Deep-learning processor design |
| 第 14 週 | Final Project:Neural-network/Deep-learning processor design |
| 第 15 週 | Final Project:Neural-network/Deep-learning processor design |
| 第 16 週 | Final project (oral presentation) |
Text: Jan M. Rabaey and Anantha Chandrakasan, Digital Integrated Circuits, A Design Perspective, 2nd edition, Prentice Hall (2003) Supplementary text: Neil H.E. Weste and David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” Fourth Edition, Addison Wesley (2011)
- 地點
- 730, Engineering building 5.
- 時間
- Tuesday: 17:30-19:30(EE730), Thursday: 16:30-18:00(EE207), or send email for an appointment
- 聯絡方式
- Email:yuhwaitseng@nycu.edu.tw Tel.:03-5712121-54440